Every serious foundry roadmap for the next four years converges on the same destination: 1.4 nanometre, gate-all-around transistors, high-numerical-aperture lithography, and a capital expenditure figure that only three companies on earth can absorb.
Cadence Silicon raised $900 million in April to build on 7nm — a node TSMC classifies as mature and prices accordingly.
The thesis is narrower than it first appears. Cadence is not arguing that smaller transistors stop mattering. It is arguing that for a specific and growing class of workload — inference at the edge, in devices with hard thermal ceilings and no fan — the binding constraint is not transistor density but memory bandwidth per watt. On that metric, the company’s engineers argue, a mature node with an aggressive on-package memory architecture beats a leading-edge node with a conventional one.
Whether that is true is an empirical question that will be settled by silicon in about eighteen months. What is already true is that the strategy has a financial logic independent of the engineering. Mature-node capacity is available, cheap and getting cheaper as the industry’s attention moves up. A company that can design around its limits acquires a cost structure its competitors cannot match.
The risk is well understood inside the company. If the memory-bandwidth thesis is wrong, or if the leading edge solves the same problem through packaging rather than process, Cadence has committed nine figures to a dead end. Its founders spent six years at a major foundry and describe the bet, without much hedging, as a wager that the roadmap has been optimised for the wrong customer.
